/*Generated header by VhdlScript2Header, made by Hartmut Schorrig, Version 2009-11-26, source org.vishia.zbnf.example.vhdlScript.java */
#ifndef __Fpga.h_h__
#define __Fpga.h_h__


typedef struct FPGA_BITCTRL_BASE_t {
  int32 BITCTRL_BASE;                                       //000000 
} FPGA_BITCTRL_BASE; 




typedef struct FPGA_STAT_REG_BASE_t {
  int32 DIG_IO_STAT;                                        //002000 
  int32 dummy00206C[26];
  int32 SYS_NOK_REASON_FIRST;                               //00206C 
} FPGA_STAT_REG_BASE; 




typedef struct FPGA_STATUS_RECEIVE_FAIL_COUNT_PM1_t {
  int32 STATUS_RECEIVE_FAIL_COUNT_PM1;                      //003000 
  int32 STATUS_RECEIVE_FAIL_COUNT_PM2;                      //003004 
  int32 STATUS_RECEIVE_FAIL_COUNT_PM3;                      //003008 
  int32 STATUS_RECEIVE_FAIL_COUNT_PM4;                      //00300C 
  int32 STATUS_RECEIVE_FAIL_COUNT_PM5;                      //003010 
  int32 STATUS_RECEIVE_FAIL_COUNT_PM6;                      //003014 
  int32 STATUS_RECEIVE_FAIL_COUNT_PM7;                      //003018 
} FPGA_STATUS_RECEIVE_FAIL_COUNT_PM1; 




typedef struct FPGA_TRIGGER_RECEIVE_FAIL_COUNT_PM1_t {
  int32 TRIGGER_RECEIVE_FAIL_COUNT_PM1;                     //003440 
  int32 TRIGGER_RECEIVE_FAIL_COUNT_PM2;                     //003444 
  int32 TRIGGER_RECEIVE_FAIL_COUNT_PM3;                     //003448 
  int32 TRIGGER_RECEIVE_FAIL_COUNT_PM4;                     //00344C 
  int32 TRIGGER_RECEIVE_FAIL_COUNT_PM5;                     //003450 
  int32 TRIGGER_RECEIVE_FAIL_COUNT_PM6;                     //003454 
  int32 TRIGGER_RECEIVE_FAIL_COUNT_PM7;                     //003458 
} FPGA_TRIGGER_RECEIVE_FAIL_COUNT_PM1; 




typedef struct FPGA_CTRL_REG_BASE_t {
  int32 EN_DEBUG_TEST;                                      //004000 
  int32 DEBUG_TEST_STAT;                                    //004004 
  int32 dummy004010[2];
  int32 HPIRQ_EN;                                           //004010 
  int32 HPIRQ_MSET;                                         //004014 
  int32 HPIRQ_MCLR;                                         //004018 
  int32 HPIRQ_QUIT;                                         //00401C 
  int32 LPIRQ_EN;                                           //004020 
  int32 LPIRQ_MSET;                                         //004024 
  int32 LPIRQ_MCLR;                                         //004028 
  int32 LPIRQ_QUIT;                                         //00402C 
} FPGA_CTRL_REG_BASE; 




typedef struct FPGA_RW_REG_BASE_t {
  int32 TMM_SYSTEM_CLOCK;                                   //005000 
  int32 CURRBASETIME_LOW;                                   //005004 
  int32 CURRBASETIME_HIGH;                                  //005008 
  int32 UM_RX_GEN_INT_COUNT;                                //00500C 
  int32 COL_TIME;                                           //005010 
  int32 REDU_DATA_SIZE;                                     //005014 
} FPGA_RW_REG_BASE; 




typedef struct FPGA_TRGBUF_t {
  int32 TRGBUF;                                             //006000 
} FPGA_TRGBUF; 




typedef struct FPGA_MI_TRGMSK_STAT_t {
  int32 MI_TRGMSK_STAT;                                     //008000 
} FPGA_MI_TRGMSK_STAT; 




typedef struct FPGA_MI_SHORT_BLOCK_TIME_t {
  int32 MI_SHORT_BLOCK_TIME;                                //00A000 
} FPGA_MI_SHORT_BLOCK_TIME; 


typedef struct FPGA_References_t {
  FPGA_BITCTRL_BASE* FPGA_BITCTRL_BASE;
  FPGA_STAT_REG_BASE* FPGA_STAT_REG_BASE;
  FPGA_STATUS_RECEIVE_FAIL_COUNT_PM1* FPGA_STATUS_RECEIVE_FAIL_COUNT_PM1;
  FPGA_TRIGGER_RECEIVE_FAIL_COUNT_PM1* FPGA_TRIGGER_RECEIVE_FAIL_COUNT_PM1;
  FPGA_CTRL_REG_BASE* FPGA_CTRL_REG_BASE;
  FPGA_RW_REG_BASE* FPGA_RW_REG_BASE;
  FPGA_TRGBUF* FPGA_TRGBUF;
  FPGA_MI_TRGMSK_STAT* FPGA_MI_TRGMSK_STAT;
  FPGA_MI_SHORT_BLOCK_TIME* FPGA_MI_SHORT_BLOCK_TIME;
} FPGA_References; 




  fPGA_References.FPGA_BITCTRL_BASE = (FPGA_BITCTRL_BASE*)(0x000000 + FPGA_BASEMEMADDR);
  fPGA_References.FPGA_STAT_REG_BASE = (FPGA_STAT_REG_BASE*)(0x002000 + FPGA_BASEMEMADDR);
  fPGA_References.FPGA_STATUS_RECEIVE_FAIL_COUNT_PM1 = (FPGA_STATUS_RECEIVE_FAIL_COUNT_PM1*)(0x003000 + FPGA_BASEMEMADDR);
  fPGA_References.FPGA_TRIGGER_RECEIVE_FAIL_COUNT_PM1 = (FPGA_TRIGGER_RECEIVE_FAIL_COUNT_PM1*)(0x003440 + FPGA_BASEMEMADDR);
  fPGA_References.FPGA_CTRL_REG_BASE = (FPGA_CTRL_REG_BASE*)(0x004000 + FPGA_BASEMEMADDR);
  fPGA_References.FPGA_RW_REG_BASE = (FPGA_RW_REG_BASE*)(0x005000 + FPGA_BASEMEMADDR);
  fPGA_References.FPGA_TRGBUF = (FPGA_TRGBUF*)(0x006000 + FPGA_BASEMEMADDR);
  fPGA_References.FPGA_MI_TRGMSK_STAT = (FPGA_MI_TRGMSK_STAT*)(0x008000 + FPGA_BASEMEMADDR);
  fPGA_References.FPGA_MI_SHORT_BLOCK_TIME = (FPGA_MI_SHORT_BLOCK_TIME*)(0x00A000 + FPGA_BASEMEMADDR);




#endif __Fpga.h_h__
